1. Field of the Invention
The present invention generally relates to methods for manufacturing semiconductor devices. More particularly, this invention relates to methods for manufacturing semiconductor devices having dual work function and to semiconductor devices made thereof.
2. Description of the Related Technology
Up to now, semiconductor industry remains driven by scaling geometric dimensions of metal-oxide-semiconductor field-effect-transistors (MOSFETs). With traditional MOSFET-technology, using silicon dioxide (SiO2) as gate dielectric and polycrystalline silicon (poly-Si) as gate material, a lot of problems occur when scaling down to 100 nm or below.
As the gate dielectric thickness is reduced, an exponential increase of gate direct tunneling currents occurs. One solution to solve this problem for a 45 nm technology node and beyond is the introduction of so-called high-k dielectrics as gate dielectric. A high-k dielectric is a dielectric featuring a dielectric constant (k) higher than the dielectric constant of SiO2, i.e. k>3.9. High-k dielectrics allow for a larger physical thickness (compared to SiO2) for obtaining a same effective capacitance than can be obtained with a much thinner SiO2 layer. The larger physical thickness of the high-k material reduces gate leakage currents.
For SiO2 oxide thicknesses below 2 nm, a polysilicon (poly-Si) depletion effect starts to become dominant in the poly-Si gate. A solution to this problem is the introduction of metals as gate material. Advantages of metal gates are elimination of the polysilicon depletion effect, very low resistance, no dopant penetration possible and better compatibility with high-k gate dielectrics.
By introducing metal gates, the threshold voltage of the MOSFET becomes controlled by the metal work function. Regarding metal gate electrodes, tuning of the work function is not straightforward as a different work function is needed for NMOS than for PMOS. This requires now a (n-type) metal (replacing poly-Si) that works for nMOSFET (i.e. a work function preferably between about 3.9 eV and about 4.4 eV) and a (p-type) metal that works for pMOSFET (i.e. a work function preferably between about 4.8 eV and about 5.2 eV). Whereas the work function of a polysilicon gate electrode can be tuned by ion implantation, the work function of a metal gate electrode is a material property which cannot be changed easily.
It has been proven difficult to identify band-edge metals (metals with either a n-type or a p-type work function (WF), required for low device voltage threshold, Vt) that are compatible with the conventional complementary metal oxide semiconductor (CMOS) fabrication process. CMOS can be made using dual metal gates with single or dual dielectrics. In either case, a selective removal of one of the metal gates is necessary and adds substantial complexity and costs to the manufacturing process. Moreover, after the selective removal process, the interface between the underlying dielectric layer and the metal electrode is often modified, due to the presence of undesired dangling bonds. This modification may influence the effective work function of the gate stack in an unwanted way.
A major challenge of implementing high-k gate dielectrics and metal gates in CMOS devices is the PMOS effective work function roll-off phenomena in the low equivalent oxide thickness (EOT) region. It remains difficult to achieve PMOS band-edge work functions for low EOT (i.e. below 1.5 nm).
There is a need for simplified integration schemes for high-k/metal gate semiconductor devices and more specifically for simplified dual work function semiconductor device integration schemes, for example for dual work function CMOS devices.